1. Field of the Invention
This invention generally relates to a circuit board and fabricating process thereof, and more particularly to a process of fabricating a circuit board using a circuit board unit with a core layer.
2. Description of the Related Art
Flip chip bonding technology is widely used for chip scale package (“CSP”). Flip Chip describes the method of electrically and mechanically connecting the die to the package carrier. The package carrier, either substrate or printed circuit board (“PCB”), and then provides the connection from the die to the exterior of the package. The interconnection between die and carrier in flip chip packaging is made through a plurality of conductive bumps that is placed directly on the die surface. The bumped die is then flipped over and placed face down, with the bumps electrically and mechanically connecting to the carrier. After the die is soldered, underfill is applied between the die and the carrier, around the solder bumps. The underfill is designed to contract the stress in the solder joints caused by the difference in thermal expansion between the silicon die and carrier.
The boom in flip chip packaging results both from the advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment, and services. Eliminating bond wires reduces the delaying inductance and capacitance of the connection by a factor of 10, and shortens the path by a factor of 25 to 100. The result is high speed off-chip interconnection. Flip chip also gives the greatest input/output connection flexibility. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Hence, Flip chip technology is suitable for high pin count package.
As for the carrier, because the rigid substrate is suitable for high-density and high-signal-count layout, flip chip bonding technology generally adopts the rigid substrate as a carrier. The most common rigid substrate processes are laminate and build-up processes. Because the carrier made by build-up processes allows a higher routing density, build-up processes on the rigid substrates are more popular.
Build-up technology uses a core layer as a base layer and forms a plurality of through holes on the core layer by mechanical drill. Then plated through hole (“PTH”) technology is used to form electrical plug inside those through holes. Dielectric layers and patterned conducting layers then are formed to form a rigid substrate. Furthermore, to electrically connect two conducting layers, openings are formed on the dielectric layer by using photo via, laser ablation and plasma etching procedures to expose the underlying conducting layer. Then the conducting materials are deposited into the openings to form the conductive vias thereby electrically connecting these two conducting layers.
However, the conventional build-up technology requires complex processes including plating, photo via, laser ablation and plasma etching procedures. Plating and photo via cause a long process cycle; the costs of laser ablation and plasma etching are relatively high.